Lattice Mapping Report File for Design Module 'i2c_master'
Design Information
Command line: map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial
i2c_master_i2c_master.ngd -o i2c_master_i2c_master_map.ncd -pr
i2c_master_i2c_master.prf -mp i2c_master_i2c_master.mrp -lpf C:/Users/22822
/Desktop/2/source/i2c_master_PCF8591_DAC/i2c_master/i2c_master_i2c_master.l
pf -lpf
C:/Users/22822/Desktop/2/source/i2c_master_PCF8591_DAC/i2c_master.lpf -c 0
-gui -msgset
C:/Users/22822/Desktop/2/source/i2c_master_PCF8591_DAC/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-4000HCCSBGA132
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.8.0.115.3
Mapped on: 12/18/17 08:38:55
Design Summary
Number of registers: 89 out of 4635 (2%)
PFU registers: 89 out of 4320 (2%)
PIO registers: 0 out of 315 (0%)
Number of SLICEs: 129 out of 2160 (6%)
SLICEs as Logic/ROM: 129 out of 2160 (6%)
SLICEs as RAM: 0 out of 1620 (0%)
SLICEs as Carry: 37 out of 2160 (2%)
Number of LUT4s: 256 out of 4320 (6%)
Number used as logic LUTs: 182
Number used as distributed RAM: 0
Number used as ripple logic: 74
Number used as shift registers: 0
Number of PIO sites used: 4 + 4(JTAG) out of 105 (8%)
Number of block RAMs: 1 out of 10 (10%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 2 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 3
Net sys_clk_12m_c: 24 loads, 24 rising, 0 falling (Driver: PIO sys_clk_12m
)
Net i2c_master_config_inst/i2c_ack[2]: 5 loads, 5 rising, 0 falling
(Driver: i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i1 )
Net clk_div_100k: 28 loads, 28 rising, 0 falling (Driver:
clk_div_inst/clk_p_29 )
Number of Clock Enables: 10
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_28: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_27: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_19: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_21: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_14: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/cnt_start_2__N_429: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_18: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_23: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_24: 2
loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_20: 1
loads, 1 LSLICEs
Number of LSRs: 15
Net i2c_master_config_inst/i2c_master_logic_inst/n5853: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4417: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4399: 4 loads, 4 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n6271: 1 loads, 1 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4403: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4422: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4424: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n6252: 1 loads, 1 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4426: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4406: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4420: 2 loads, 2 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n6224: 1 loads, 1 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n5123: 1 loads, 1 LSLICEs
Net i2c_master_config_inst/i2c_master_logic_inst/n4269: 1 loads, 1 LSLICEs
Net clk_div_inst/n4410: 17 loads, 17 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_4: 23 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_2: 22 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_5: 22 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_0: 19 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_6: 18 loads
Net clk_div_inst/n4410: 17 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_13: 17 loads
Net i2c_master_config_inst/i2c_master_logic_inst/clk_div_100k_enable_19: 16
loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_1: 16 loads
Net i2c_master_config_inst/i2c_master_logic_inst/state_current_3: 16 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
No errors or warnings present.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| rst_n | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| sys_clk_12m | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| scl | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| sda | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
Signal i2c_master_config_inst/i2c_master_logic_inst/n6652 was merged into signal
sda_r
Signal n3577 was merged into signal
i2c_master_config_inst/i2c_master_logic_inst/sda_ctl
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_10/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_10/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_20/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_20/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_22/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_22/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_2/S1 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_2/S0 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_2/CI undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_24/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_24/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_16/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_16/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_26/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_26/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_28/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_28/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_18/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_18/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_30/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_30/CO undriven or does not drive anything -
clipped.
Signal clk_div_inst/cnt_p_1107_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/cnt_p_1107_add_4_1/CI undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_4/S1 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_4/S0 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_8/S1 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_8/S0 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_6/S1 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_6/S0 undriven or does not drive anything - clipped.
Signal clk_div_inst/add_3715_12/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_12/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_14/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/add_3715_14/S0 undriven or does not drive anything -
clipped.
Signal clk_div_inst/cnt_p_1107_add_4_33/S1 undriven or does not drive anything -
clipped.
Signal clk_div_inst/cnt_p_1107_add_4_33/CO undriven or does not drive anything -
clipped.
Signal i2c_master_config_inst/wave_rom_address_1108_add_4_1/S0 undriven or does
not drive anything - clipped.
Signal i2c_master_config_inst/wave_rom_address_1108_add_4_1/CI undriven or does
not drive anything - clipped.
Signal i2c_master_config_inst/wave_rom_address_1108_add_4_9/S1 undriven or does
not drive anything - clipped.
Signal i2c_master_config_inst/wave_rom_address_1108_add_4_9/CO undriven or does
not drive anything - clipped.
Block i2c_master_config_inst/i2c_master_logic_inst/i1868_4_lut_then_1_lut was
optimized away.
Block i2c_master_config_inst/i2c_master_logic_inst/i1428_1_lut was optimized
away.
Block i1 was optimized away.
Block i2 was optimized away.
Memory Usage
INFO: Design contains EBR with GSR enabled. The GSR is only applicable for
output registers except FIFO.
/rom_waveform_inst:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR rom_waveform_0_0_0: TYPE= DP8KC, Width_A= 8, Depth_A= 256,
REGMODE_A= OUTREG, REGMODE_B= NOREG, RESETMODE= SYNC,
ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL,
GSR= ENABLED, MEM_INIT_FILE= rom_waveform.mem, MEM_LPC_FILE=
rom_waveform.lpc
ASIC Components
---------------
Instance Name: rom_waveform_inst/rom_waveform_0_0_0
Type: DP8KC
GSR Usage
---------
GSR Component:
The Global Set Reset (GSR) resource has been used to implement a global reset
of the design. The reset signal used for GSR control is 'rst_n_c'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------
These components have the GSR property set to ENABLED and the local reset
is synchronous. The components will respond to the synchronous local reset
and to the unrelated asynchronous reset signal 'rst_n_c' via the GSR
component.
Type and number of components of the type:
Register = 68
DP8KC = 1
Type and instance name of component:
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1109__i0
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i3
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i4
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_write_reg_data_11
11__i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_write_reg_data_11
11__i3
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i2
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i6
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i13
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1109__i3
Register : i2c_master_config_inst/i2c_master_logic_inst/i2c_ack__i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i2
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_write_reg_data_11
11__i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1110__i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1110__i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1110__i3
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_r_addr_i0_i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_w_data_i0_i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_addr_i0_i1
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i7
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i5
Register : i2c_master_config_inst/i2c_master_logic_inst/state_current__i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_start_i0_i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_write_reg_data_11
11__i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_w_data_i0_i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_ack_w_data_i0_i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_reg_addr_1110__i0
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1109__i1
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_stop_i0_i2
Register : i2c_master_config_inst/i2c_master_logic_inst/cnt_dev_addr_1109__i2
Register : clk_div_inst/cnt_p_1107__i30
Register : clk_div_inst/cnt_p_1107__i29
Register : clk_div_inst/cnt_p_1107__i28
Register : clk_div_inst/cnt_p_1107__i27
Register : clk_div_inst/cnt_p_1107__i26
Register : clk_div_inst/cnt_p_1107__i25
Register : clk_div_inst/cnt_p_1107__i24
Register : clk_div_inst/cnt_p_1107__i23
Register : clk_div_inst/cnt_p_1107__i22
Register : clk_div_inst/cnt_p_1107__i21
Register : clk_div_inst/cnt_p_1107__i20
Register : clk_div_inst/cnt_p_1107__i19
Register : clk_div_inst/cnt_p_1107__i18
Register : clk_div_inst/cnt_p_1107__i17
Register : clk_div_inst/cnt_p_1107__i16
Register : clk_div_inst/cnt_p_1107__i15
Register : clk_div_inst/cnt_p_1107__i14
Register : clk_div_inst/cnt_p_1107__i13
Register : clk_div_inst/cnt_p_1107__i12
Register : clk_div_inst/cnt_p_1107__i11
Register : clk_div_inst/cnt_p_1107__i10
Register : clk_div_inst/cnt_p_1107__i9
Register : clk_div_inst/cnt_p_1107__i8
Register : clk_div_inst/cnt_p_1107__i7
Register : clk_div_inst/cnt_p_1107__i6
Register : clk_div_inst/cnt_p_1107__i5
Register : clk_div_inst/cnt_p_1107__i4
Register : clk_div_inst/cnt_p_1107__i3
Register : clk_div_inst/cnt_p_1107__i2
Register : clk_div_inst/cnt_p_1107__i1
Register : clk_div_inst/cnt_p_1107__i0
Register : clk_div_inst/cnt_p_1107__i31
DP8KC : rom_waveform_inst/rom_waveform_0_0_0
EBR components with enabled GSR
-------------------------------
These EBR components have the GSR property set to ENABLED. The components
will respond to the asynchronous reset signal 'rst_n_c' via the GSR
component.
Type and number of components of the type:
DP8KC = 1
Type and instance name of component:
DP8KC : rom_waveform_inst/rom_waveform_0_0_0
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 50 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights
reserved.